Search - vhdl multiplier

[VHDL-FPGA-Verilog] 8bit-Shift-and-Adder--multiplier

Description: 8位乘法器，经移位相加算法来实现的，用的VHDL语言-8-bit multiplier, adding the algorithm to realize the shift of
Platform: | Size: 584704 | Author: Aaran | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 4位乘法器 vhdl library IEEE use IEEE.std_logic_1164.all entity one_bit_adder is port ( A: in STD_LOGIC B: in STD_LOGIC C_in: in STD_LOGIC S: out STD_LOGIC C_out: out STD_LOGIC ) end one_bit_adder -4-bit multiplier vhdl library IEEE use IEEE.std_logic_1164.all entity one_bit_adder is port (A: in STD_LOGIC B: in STD_LOGIC C_in: in STD_LOGIC S: out STD_LOGIC C_out: out STD_LOGIC) end one_bit_adder
Platform: | Size: 1024 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] mult

Description: 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete the functional design of the multiplier, and Modelsim for simulation by verification.
Platform: | Size: 4096 | Author: xiu | Hits:

[VHDL-FPGA-Verilog] chengxu

Description: 4位乘法器，4位除法器，K倍频的VHDL实现-Four multipliers, four dividers, K multiplier of VHDL
Platform: | Size: 2048 | Author: 郭慧 | Hits:

[VHDL-FPGA-Verilog] VHDL-test-codeBooth-multiplier

Description: VHDL实验代码：Booth乘法器，是一个基于VHDL语言开发的程序，非常的实用-VHDL test code: Booth multiplier, is a VHDL-based language development program, a very practical
Platform: | Size: 1024 | Author: Johonson | Hits:

[VHDL-FPGA-Verilog] DESIGN-AND-IMPLEMENTATION-OF-DIFFERENT-MULTIPLIER

Description: DESIGN AND IMPLEMENTATION OF DIFFERENT MULTIPLIERS USING VHDL
Platform: | Size: 379904 | Author: Christoffer | Hits:

[VHDL-FPGA-Verilog] Sixteen-hardware-multiplier

Description: vhdl 编学基于移位相加的16位硬件乘法器。-vhdl
Platform: | Size: 2016256 | Author: 陈凡 | Hits:

[VHDL-FPGA-Verilog] 67719585-Booth-Multiplier-Vhdl-Code

Description: vhdl code for booth multiplier-vhdl code for booth multiplier...........................
Platform: | Size: 10240 | Author: satya | Hits:

[VHDL-FPGA-Verilog] 100-vhdl-examples

Description: 资料中包含了100个VHDL语言开发范例，如：加法器、乘法器、比较器、二路选择器、寄存器、综合单元库、函数、七值逻辑线或分辨函数-The data contains 100 examples of VHDL language development, such as: adder, multiplier, comparator, double-selection, register, comprehensive cell library, function, seven-value logic line, or distinguish function.
Platform: | Size: 642048 | Author: 东方不败 | Hits:

[VHDL-FPGA-Verilog] 4-x-4-on-time-multiplier--table

Description: 4×4 查找表乘法器 vhdl 语言描述-4 x 4 on time-multiplier look-up table VHDL language describe
Platform: | Size: 252928 | Author: 郭少华 | Hits:

[Communication-Mobile] Booth-Multiplier-VHDL-Code

Description: 布斯乘法器 Booth Multiplier VHDL Code-Booth Multiplier VHDL Code
Platform: | Size: 5120 | Author: li | Hits:

[VHDL-FPGA-Verilog] VHDL_Bough_64-bit-twos-complement-multiplier

Description: VHDL Ccode_Booth two s complement multiplication
Platform: | Size: 2048 | Author: mahsa | Hits:

[VHDL-FPGA-Verilog] 4-bit-Multiplier

Description: IT is a 4 bit multiplier vhdl coding file which is run in altera quatrs - II. in which 4 binary bit is multiplied and waveform can be obtained
Platform: | Size: 47104 | Author: Henal patel | Hits:

[Other] 8bit-multiplier

Description: 8位二进制数乘法器VHDL实现8位二进制数乘法器设计，乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。 -8-bit binary multiplier VHDL 8-bit binary multiplier design, multiplication by itemized shift sum principle, starting from the least significant bit of the multiplicand 1, the multiplier the left after the last and addition if it is 0, to 0 after adding the left until the most significant bit of the multiplicand.
Platform: | Size: 2048 | Author: 李谦 | Hits:

[Industry research] Vhdl-Implementation-of--Fast-32x32-Multiplier-Bas

Description: The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra is presented. The existing method is 16*16 bit multiplication in relatively less speed. The proposed method is 32*32 bit multiplication in terms of relatively high speed, low power, less area and less delay. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modelling. This also gives chances for modular design where smaller block can be used to design the bigger one.-The Vedic mathematics is quite different from conventional method of multiplication like adder and shifter. This mathematics is mainly based on sixteen principles. The multiplier (referred henceforth as Vedic multiplier) architecture based on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra is presented. The existing method is 16*16 bit multiplication in relatively less speed. The proposed method is 32*32 bit multiplication in terms of relatively high speed, low power, less area and less delay. This will help in designing multiplier in VHDL, as its give effective utilization of structural method of modelling. This also gives chances for modular design where smaller block can be used to design the bigger one.
Platform: | Size: 172032 | Author: farbosein | Hits:

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